The present invention generally relates to an electrical arrangement, and more particularly, to a redundant circuit for a memory circuit having a plurality of memory cell blocks. A redundant memory cell of one block is arranged to be capable of commonly serving as a redundant memory cell of another block.
In memory circuits, it is conventional to divide a memory cell into a plurality of blocks for various reasons. An example is shown in FIG. 3, where a conventional circuit arrangement includes a memory circuit having normal memory cell blocks 7 and 8, redundant memory cells blocks 1 and 2 for the memory cell blocks 7 and 8, decoder 9, redundancy decoders 5 and 6 coupled with the redundant memory cell blocks 1 and 2, and a block signal generating circuit 10 coupled with the decoder 9. Thus, it is necessary to provide the redundant memory cell blocks 1 and 2 and the redundancy decoders 5 and 6 for generating selecting signals on lines 3 and 4 for the redundant memory cell blocks 1 and 2 for relieving a faulty memory cell.
In the conventional circuit arrangement as described above, however, since a block selecting signal on line 11 of the block signal generating circuit 10 for the decoder 9 which produces the selecting signal with respect to the memory cell blocks 7 and 8 is not controlled by the redundant memory cell selecting signals on lines 3 and 4, the respective blocks 7 and 8 are required to have the redundant memory cell blocks 1 and 2. This structure requires the corresponding redundancy decoders 5 and 6, thus complicating the circuit construction, which is not a desirable feature.